library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logica is
Port ( microinst : in STD_LOGIC_VECTOR (1 downto 0);
cc : in STD_LOGIC;
pl : out STD_LOGIC;
smap: out STD_LOGIC;
--vect: out STD_LOGIC;
selector: out STD_LOGIC);
end logica;

architecture Behavioral of logica is
begin
process(microinst,cc)
begin
if(microinst="00") 
	then 	selector <= '0';
			pl <= '1';
			smap <= '1';
	--		vect <= '1';
elsif(microinst="01") 
			then if(cc='0') 
					then	selector <= '1';
							pl <= '0';
							smap <= '1';
		--					vect <= '1';
					elsif(cc='1') then
							selector <= '0';
							pl <= '1';
							smap <= '1';
			--				vect <= '1';
			end if;

elsif(microinst="10") 
			then  selector <= '1';
					pl <= '1';
					smap <= '0';
				--	vect <= '1';

elsif(microinst="11") 
			then if(cc='0') 
					then	selector <= '1';
							pl <= '1';
							smap <= '1';
					--		vect <= '0';
					elsif(cc='1') then
							selector <= '0';
							pl <= '1';
							smap <= '1';
						--	vect <= '0';
			end if;

end if;
end process;

end Behavioral;